Antona Application Note
ANC-3052B for I2C Control
title Video Scan Memory Write Timing Generator - VID1
pattern Vidwr
revision K
author Robert Mikkelson
company Antona Corporation
date 10/23/94
chip Vidwr gal16v8
; pin 1 2 3 4 5 6 7 8 9 10
CLK CT1 CT2 CT3 CT4 CT5 CT6 CT7 CT8 GND
; pin 11 12 13 14 15 16 17 18 19 20
/EO SW3 BOT CT0 VDR MDS MSV MW1 MW2 VCC
; Electronic signature for this part - "VIDW #01"
@UES VIDWR
equations
; Select which line buffer to store to
/MW1 = /CT0 * /MSV
/MW2 = CT0 * /MSV
; Start SAVING memory RGB when line 22 comes up. This will insure
; that the 1st line is the top of frame.
/MSV := /CT8 * /CT7 * /CT6 * /CT5 * /CT4 * CT3 * CT2 * CT1 * CT0 +
/BOT * /MSV
; Start DISPLAYING memory RGB at start of line 23.
; MDS used by VID2 for blanking top and bottom of screen
/MDS := /CT8 * /CT7 * /CT6 * /CT5 * CT4 * /CT3 * /CT2 * /CT1 * /CT0 +
/BOT * /MDS
; Stop DISPLAYING memory RGB at end of frame for 60 and 48 Hz mode
;
; SW3 HIGH => 48 = 141H, 321 lines of data X2 = 642, (655/24)
; SW3 LOW => 60 = 100H, 256 lines of data X2 = 512, (525/30), 480 LINES
BOT = CT8 * /CT7 * CT6 * /CT5 * /CT4 * /CT3 * /CT2 * /CT1 * CT0 * SW3+
CT8 * /CT7 * /CT6 * /CT5 * /CT4 * /CT3 * /CT2 * /CT1 * /CT0 * /SW3
; Vertical Drive pulse, 420 usec total length
/VDR := /CT8 * /CT7 * /CT6 * /CT5 * /CT4 * /CT3 * /CT2 * /CT1 * /CT0 +
/CT2 * /VDR
; + CT1 * /VDR
; end of file
;--------------------------------------------------------------------------------------------
title Video Scan Memory Read/2X Timing Generator - VID2
pattern Vidrd
revision L
author Robert Mikkelson
company Antona Corporation
date 11/07/94
chip Vidrd gal16v8
; pin 1 2 3 4 5 6 7 8 9 10
CLK CT0 CT1 CT2 CT3 CT4 CT5 CT6 CT7 GND
; pin 11 12 13 14 15 16 17 18 19 20
EON CT8 HD L21 RST BLK HZ2 SW1 TST VCC
; Electronic signature for this part - "VIDR #02"
@UES VIDRD
equations
; Reset up counter to produce 2nd (middle) Horizontal Drive pulse
; when HD counts up to 186H or 390 x 81 ns = 31.78 us (63.492us/2)
; NTSC signal generates 1st pulse with HD input.
RST = CT0 * /CT1 * CT2 * /CT3 * /CT4 * /CT5 * /CT6 * CT7 * CT8 * SW1 +
/CT0 * CT1 * CT2 * /CT3 * /CT4 * /CT5 * /CT6 * CT7 * CT8 * /SW1 +
HD
; Start line memory output when clock state = 0 is detected (created by RST)
; then stop when state 64 (5 us) is counted to produce Blanking pulse
; 'L21'(horizontal line 21) is the blanking for the top of the frame
/BLK := /CT8 * /CT7 * /CT6 * /CT5 * /CT4 +
/CT5 * /BLK + /CT4 * /BLK + L21
; /CT6 * /BLK + L21
; Double speed horizontal drive pulse for output (SYNC X2)
; start when 10th state starts (800ns)
; stop when 24th state starts (2.5us)
/HZ2 := CT0 * CT1 * CT2 * CT3 * /CT4 * /CT5 * /CT6 * /CT7 * /CT8 +
/CT5 * /HZ2 + CT4 * /HZ2 + CT3 * /HZ2 + /CT2 * /HZ2 + CT1 * /HZ2
; generate a pulse close to the middle of a double scan
; generate a pulse just after raising edge of /HZ2
TST = /CT8 * /CT7 * /CT6 * CT5 * CT4 * /CT3 * /CT2
; end of file
Related Links
- Return to Body of Application Note
- Datasheet on ANC-3052B Embedded Adapter® Single Board Computer
- PDF formatted ANC-3052B User's Manual
- Datasheet on ANC-7852 STD BUS 8052 Single Board Computer
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Updated 05/27/02 12:00